AADL Inspector is a model processing framework for Critical Software Architecture Models. Based on the most recent version of the SAE-AS5506 (AADL) standard, it embeds a set of timing analysis, simulation and code generation tools. The tool also provides customizable input model converters for UML profiles or Domain Specific Modelling Languages.
The current version of AADL Inspector (v1.9) encompasses the following features:
- AADL support
- AADL Project browser
- Syntactic analysis (aadlrev)
- AADL v2.3 (AS-5506D)
- AADL Behavior Annex v2.0 (AS-5506/2A Annex D)
- AADL Error Model Annex v2.0 (AS-5506/1A Annex E)
- AADL ARINC 653 Annex (AS-5506/1A Annex A)
- AADL FACETM Annex (AS-5506/4 Annex F)
- Converts older AADL models into v2.2 (with a few restrictions on property associations)
- Import of AADL libraries from GitHub
- Models import/export (powered by LAMP)
- SysML v1 import
- FACE 3.0 import
- Capella Physical Architecture import
- Generic XML/XMI/CSV import
- HOOD/SIF export
- AADL template models:
- Multi tasks (Real-Time Scheduling)
- Multi partitions (Time and Space Partitioning)
- Multi processors (Network Communication)
- Multi cores (Partitioned Scheduling)
- LAMP annex (Custom Model Processing)
- Static rules analysis plugins
- AADL reverse engineering
- AADL instance model graphical editor
- Round-trip engineering with Stood for AADL
- Assurance cases online verification
- Logical AADL Model Processing (LAMP) online prolog engine
- Predefined libraries to access AADL model entities
- LAMP Annexes in AADL packages (verification rules)
- LAMP Annexes in AADL components (verification goals)
- Timing analysis
- Schedulability analysis
- Turnkey integration of the CHEDDAR v3 analysis kernel
- AADL to Cheddar model transformation
- Enhanced output format for post-processing
- VCD (Value Change Dump) file output of the scheduling static simulation
- Dynamic simulation
- Turnkey integration of the MARZHIN v2 Multi-Agents simulation engine, developed in collaboration with Virtualys.
- Emulation of the AADL run-time (multi-core, multi-processor and multi-partition architectures)
- Display of dynamic time-lines for Processors, Buses, Processes, Threads and Shared Data
- Asynchronous user interaction: in and out events and data
- Simulation scenarios (input ports) and probes (output ports)
- VCD (Value Change Dump) file output of the simulation trace
- Response time analysis
- Scheduling Aware end to end Flow Latency Analysis (SAFLA)
- Schedulability analysis
- Safety & Security analysis
- Generation of Open PSA file from EMV2
- Fault Tree Analysis with Arbre Analiste
- Customizable security rules checker
- Model Properties spreadsheet
- Extracts main RT properties from all the Thread instances
- Software to Hardware allocation
- PDF documentation generator
- Ada and C code generators (Ocarina)
- Tool customization capabilities
- "plug and check" analysis tools
- Scripting language for plugins definition
- Command line options
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- AI1.8.PNG (258.9 KB ) - added by 2 years ago.
- AI1.8-overview.png (124.8 KB ) - added by 2 years ago.
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please refer to: https://www.arbre-analyste.fr/en.html
- inspector9brochure.pdf (1.1 MB ) - added by 6 months ago.
- AI1.9-overview.png (275.1 KB ) - added by 6 months ago.
- AI1.9.PNG (219.6 KB ) - added by 6 months ago.
- AI User Manual.pdf (2.4 MB ) - added by 6 months ago.
- AADLInspector1.9QuickStart.pdf (1.4 MB ) - added by 6 months ago.